Tanner EDA 最新版本V13现已发布

Hierarchy Navigator

A Hierarchy Navigator is now available in S-Edit for easy navigation through the cell

hierarchy. Counts of parents (cell the specified cell is instanced in) and children (cells

contained within the specified cell) of a cell are listed. It is also possible to view (and

count) all ancestors and descendants of a cell.

Hierarchical Find

A new "Hierarchical Find" dialog is available in S-Edit. This dialog searches for

specified objects through the hierarchy, and allows stepping through each object one

at a time. Cells and Views are opened automatically when an object is found in a

new view. Scripts allow for detailed specification of search criteria. Scripts also

facilitate actions that can be applied to modify found objects.

Library Navigator

An option to sort cells by modified date is added to the Library Navigator.

Other S-Edit Enhancements

A new option is added to Setup > Preferences > Selection called “Trace nets on push

and pop context” to enable/disable highlighting of selected nets when pushing into or

popping out of views. Turning off this option can improve push/pop performance on

large designs.

Cells can now be instanced by drag-and-drop from the Library navigator's cell list.

Mouse scroll wheel can now be made to scroll instead of zoom.

Verilog netlists can now be imported into S-Edit. Use File > Import > Import Verilog.

Bug Fixes

Verilog export now properly exports arrays without exploding them into individual

nets.

Performance improvements in saving designs and loading EDIF.

The SPICE setup window can now be closed without setting an analysis type.

The "property get" tcl command returns properties as strings. A -double option is

added which returns the value as a number. It returns an error if the numeric

conversion fails (or if the property does not exist).

The order of properties in the EDIF file is now consistent across multiple design

saves. This fixes unnecessary changes flagged when using revision control tools on

the design database.

Fixed problems in current annotation.

Extra views are no longer exported when exporting EDIF for a specified cell and

hierarchy.

Opening a new schematic in a new window now opens to full view

Custom toolbars are now saved between sessions.

Cells in a design are now prevented from being instanced in library.

Push In / Pop Out problems with multiple pages are fixed.

Copy Cell now displays the new cell after copy

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Known Issue

When cross-probing and back-annotating subcircuit pin currents and charges for

subcircuits which are external to S-Edit (ie. defined in T-Spice model libraries), if a

net is attached to more than one boundary pin of a subcircuit, then the displayed

current (or charge) will be the sum of the currents through all of those pins.

What's New in T-Spice v13.00

Verilog-A

The new Verilog-A interface enables users to easily create and simulate compact

device models and behavioral models. The T-Spice Verilog-A language complies

with all analog portions of the Verilog-AMS 2.2 language specification. For further

information, please read the installed manuals: Verilog-A Language Reference and

Verilog-A User Guide

User Interface Improvements

Simulation now runs on the active Spice file when the “Run Simulation” button is

pressed. The “Run Simulation” dialog has been removed, and simulation settings are

now specified in the Simulation > Simulation Settings dialog. Names of output

files are auto-generated from the input filename, and can be optionally placed in a

new folder with a timestamped name each time the simulation is run.

A new command, File > Open Folder Containing filename, will open a Windows

Explorer window where the Spice file is located.

Input files or result files may be easily Diff’ed by selecting the jobs in the Simulation

Manager, right-clicking and selecting one of the Diff options. A 3rd party Diff program

must be specified in the Simulation Settings dialog.

Built-In Device Models

The T-Spice built-in device models are now distributed as a collection of external

Dynamically Linkable Libraries (DLLs) located in the tspicemodels subdirectory of

the installation. The modularization of all transistor models improves the

performance, quality, and features of our device models: BSIM3, BSIM4, RPI TFT,

Bipolars, etc.

Known Issues

There are known issues with convergence and performance for the Verilog-A

examples, due to problems in the Verilog-A models.

In some cases, T-Spice performance has slowed down since v12.6. Performance will

be improved in the next release.

What's New in W-Edit v13.00

There are no new features in W-Edit v13.00.

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What's New in L-Edit Pro v13.00

X-Ref Cells

X-Ref cells, which provide the ability to link to cells in another tdb file, have been

modified to point directly to the final target cell in a chain of references. For example,

if File1:Cell(A) instances File2:Cell(B), and File2:Cell(B) instances File3:Cell(C), then

File1 will point directly to File3:Cell(C). The new architecture eliminates the need for

multiple copies of X-Ref cells that can occur when multiple levels designs are used.

X-Ref design links will be broken when opening designs from prior to v13. To relink

an old design, you only need to relink the Xref file in Setup Design > Xref files, you

do not need to update links on a cell by cell basis. X-ref Cells now take the name

"cellname:libname".

Assign Instance Names

Names may be assigned to instances using Cell > Assign Instance Names.

Instance names may be assigned names either in i) selections, ii) current cell, ii)

current cell and hierarchy, or iv) all cells.

Schematic Driven Layout

The SDL Navigator now has three views, By Net, By Instance, and By Unrouted

Segment. By Net shows the list of nets, with the list of pins expandable under each

net. By Instance shows the list of instances, with the list of ports and the nets

connected to those ports expandable under each instance. By Unrouted Segment

shows the list of segments not completed by the autorouter.

Verilog netlists may now be imported into SDL

SDL Autorouter

New to v13, Schematic Driven Layout now contains an automatic routing capability.

The router supports any number of layers, with user specified width and spacing

rules for each layer. Keepouts may also be specified on a per layer basis. The user

may choose to route the entire netlist, or only selected nets. Incremental routing is

supported by allowing nets to be ripped-up and re-routed as needed. Manual routing

may be integrated with auto routing by identifying the active net prior to manual

routing.

The autorouter is currently in Beta release. Contact Tanner EDA Sales if you are

interested in becoming a Beta site.

LVS

Asymmetrical mosfets (M, B, J and Z) and BJTs are now supported. A default

polarization can be specified for FETs, BJTs, R, C and L, and exceptions to the

default can be specified (by model name).

Parsing .lib files when folder has space now works.

Drag and drop of VDB files into LVS is now available.

Bug Fixes

Arraying instances by stretching may now be enabled or disabled using the Instance

Stretching option in Setup Application > General tab.

Implicit Selection is now an option on the Setup Application > Selection tab.

Highlighting implicit selections is also an option.

Paste buffer is no longer cleared after using Setup Layer Palette dialog

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Fixed occasional crashes in Nudge of multiple selections.

Import Virtuoso Setup now allows listing all files using *.* in the browse dialog.

Sorting in cell open dialog is improved.

Setup Standard DRC dialog is now resizable

Fixed problems with LCell_GenerateLayers_v11_10.

Crash in LVS when exporting a batch file is fixed.

What's New in HiPer Verify v13.00

HiPer Verify provides a significant advancement in v13 with the introduction of Calibre and

Dracula compatible netlist extraction. HiPer Verify can extract a spice netlist from layout using a

Calibre or Dracula format command file, with performance significantly faster than Tanner

Standard Extract. The built in set of devices for MOS transitors, capacitors, resistors, and diodes

are supported for both Calibre and Dracula command files. User specified devices with user

written code is also supported with Calibre command files.

Labels may be used to name nets in the output Spice file. Warnings are issued to the Extract

Summary Report for different nets with the same label and the same net with different labels.

Subcircuits in the Spice file are written using instance names from L-Edit. Use Cell > Assign

Instance Names to name all the instances in the design at once.

Calibre® Compatible Netlist Extraction

Calibre commands supported for netlist extraction are:

DEVICE — Specifies how devices are recognized and how properties are computed

for a device.

LVS GROUND NAME — Specifies a list of ground names, used in net name conflict

resolution.

LVS POWER NAME — Specifies a list of power names, used in net name conflict

resolution.

LVS NETLIST COMMENT CODED SUBSTRATE — Specified whether netlists

should be written using the comment-coded parameter $SUB to represent substrate

pins in 3-pin diodes, 3-pin capacitors, and 3-pin resistors

Calibre® Compatible DRC

A list of DEFINE variables may now be set in the DRC Setup dialog. To define a

variable as TRUE, simply enter that name, to assign a value, use Name=Value

The PUSH command is now supported in HiPer Verify.

Connectivity operations are now supported on edge layers.

Bug Fixes

HiPer Verify command file parser can now handle large deeply nested implicit layer

definitions.

The single layer INT operation now only compares edges from the same polygon for

edge layer input. Polygon input was working correctly, but not edge input. This will

eliminate certain false errors from the INT operation on edge layers.

Polygon containment tests are now performed correctly for edge layer input. This will

eliminate certain false errors on INT, EXT and ENC commands.

Obtuse angle violations on DRC checks are now correctly found. They were

previously not found.

Expand Edge Outside By now parses correctly.

Implicit layer definitions now work correctly in the STAMP command.

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ATTACH, CONNECT, LABEL ORDER, and SCONNECT with DIRECT option are

now ignored. Direct verification set commands are not run in Calibre.

Fixes to SCONNECT and STAMP are made.

Secondary keywords may now be used as layer names in any operation, except the

operation itself that uses that name as a secondary keyword. Many layer names that

would previously cause errors are now allowed.

The secondary keyword INTERSECTING is now allowed as an abbreviation of

INTERSECTING ONLY.

Problems with NET AREA RATIO commands split over multiple lines are fixed.

Problems when using WITH WIDTH in a rule deck with DRC INCREMENTAL

CONNECT YES are fixed.

Parsing of include file paths is fixed.

"Negative Edge output is now working correctly for edge input layers, for example

Rule { EXT (Layer1) Layer2 <= d } where Layer1 is an edge layer.

TOUCH and NOT TOUCH with constraints are now working correctly.

WITH WIDTH now supports the != constraint.

Parser correctly handles auxiliary layers placed after NETLIST ELEMENT in a

DEVICE statement.

TRUNCATE is now allowed as well as TRUNC in the extract property language.

The EXCLUDE SHIELDED option in INT, EXT, and ENC is now parsed and ignored.

A problem with EXPAND EDGE is fixed.

False errors reported by ENCLOSE with constraints is fixed.

Missing errors on EXT with PERPENDICULAR ONLY option is fixed.

SCONNECT now reports hierarchical results without unnecessary flattening.

Incorrect results on RECTANGLE operation with >= constraint is fixed.

False errors in INSIDE operation are fixed.

Dracula® Compatible Netlist Extraction

Dracula commands supported for netlist extraction are:

ELEMENT BJT

ELEMENT CAP

ELEMENT DIO

ELEMENT LDD

ELEMENT MOS

ELEMENT RES

The following commands are not currently supported:

ELEMENT BOX

ELEMENT PAD

EQUATION

LEXTRACT

PARAMETER CAP

PARAMETER RES

Dracula® Compatible DRC

Dracula parser no longer warns for system commands that do not affect results.

Conjunctive rules involving WIDTH operation are fixed.

What's New in HiPer PX v13.00

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HiPer-PX is a new tool for accurate modeling of parasitics. Parasitic resistances within

conductive layers (metals, diffusions and polysilicons) are calculated, as are capacitances

between structures on the same and on different layers. Also, substrate capacitance as well as

substrate resistance can be extracted. HiPer PX is a physics-driven extractor, in which a field

solver uses the 3-D physical dimensions of the objects, together with their electrical and

dielectrical characteristics, to calculate these parasitics. Both finite element and boundary

element calculations are performed. Also, the extractor operates in either 3-D or 2-D modes; the

latter is fast and hierarchical, and can use precomputed 3-D models for user-specified cells. To

run HiPer PX invoke Tools > Parasitic Extractor.

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Additional Information

Minimum System Requirements

Microsoft® Windows XP, Windows Vista™

Intel® Pentium® 4 processor or Pentium 4 equivalent with SSE support

512 MB RAM

100 MB of available disk space with an additional 100 MB during installation

A video card with at least 64 MB of memory

3 button mouse

Recommended System Requirements

Microsoft® Windows Vista™

Dual Core Intel® Xeon® 2.66 GHz or better processor for desktops

Intel® Core™ 2 Duo 2.00 GHz or better processor for laptops

2 GB RAM

100 MB of available disk space with an additional 100 MB during installation

A video card with at least 256 MB of dedicated memory

Microsoft® Intellimouse

1280 x1024 Resolution - True Color (24-bit)

Installation

Install Tanner Tools from the Windows operating system. To begin, insert the distribution CD into

your CD-ROM drive. The setup program should start automatically; if it does not, then you should

navigate to the main CD directory from a file browser window, and double click SETUP.EXE to

run setup. The Tanner Tools setup program will provide information on how to proceed.

Administrator Privileges are required to install Tanner Tools v13. Power users are no longer able

to install Tanner Tools, as they could in previous versions.

Licensing

Tanner Tools is licensed software; to use the program, you must have a license from Tanner

Research, Inc. Tanner Tools will verify the license either from License Server, installed on your

company network, or from a hardware lock attached to your computer's parallel port. Tanner

Tools is available in node- or network-locked licensing.

When using the Interlink or LapLink utilities over the same port as the Tanner Research

Sentinel C-Plus-B hardware lock, the user must first remove the hardware lock from the parallel

port. This must be done in order to keep the Sentinel C-Plus-B lock functional.